The development of integrated circuit (IC) manufacturing requires fabrication of many different kinds of devices including transistors, resistors, and capacitors, as well as features patterned in various conducting layers which serve as resistive connectors (and are hence considered as resistor devices). In order to tune the manufacturing process to maximize yield, some classes of test devices are fabricated in very large numbers and exhaustively tested in order to find relatively rare failure events. Yield improvement can therefore be expensive from the standpoint of both consumed mask area and overall test time due to such large device sample sizes.
Improved characterization approaches have sought to decrease mask area and maximize the number and variety of structures testable at wafer level by creating addressable arrays of test devices. Wafer level test refers to the measurement of test devices by direct contact of measurement probes to large metal islands (i.e., probe pads) on the silicon wafer. An array of test devices uses either passive or active circuitry to selectively access (address) which device is to be tested. An array of devices can then share a common set of probe pads and improve mask density by orders of magnitude over conventional types of test devices which possess dedicated probe pads for wafer level test. Devices which are not selected for test are electrically isolated from the measurement nodes of the circuitry.
Early addressable array designs focused on characterization of simple devices such as interconnect and contacts. More sophisticated array designs included active test devices such as MOSFETs and even ring oscillators and capacitors.
Since the advent of quarter micron technology generation of silicon CMOS, increased attention has been given to array-based device testing as a means to characterize inherent variability in the IC manufacturing process. In contemporary sub-100 nm CMOS technologies, variability has become an acute problem demanding thorough statistical study using array-based approaches.
Various types of prior art devices have established dense test arrays for active and passive devices, ring oscillators, and proposed sets of test device types and sizes for elucidating variability parameters of the manufacturing process. Electrical testing is performed on each individually addressed element using conventional measurement techniques (e.g., force/sense, or Kelvin methods). Cost associated with mask area is reduced due to the high test device density achieved, but test time cost remains prohibitive.
What is needed is a current-based measurement approach to enable a highly dense test cell in order to minimize mask area and to also support a simultaneous test mode whereby a subset of devices are tested simultaneously. In this manner, a highly accelerated test capability is achieved which allows a flexible tradeoff between statistical resolution and test time.